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MP7610
Octal 14-Bit DAC ArrayTM D/A Converter with Output Amplifier and Serial Data/Address mP Control Logic
June 1998-3
FEATURES * * * * * * * * * * Eight Independent 14-Bit DACs with Output Amplifiers Low Power 320 mW (typ.) Serial Digital Data and Address Port (3-Wire Standard) 14-Bit Resolution, 12-Bit Accuracy Extremely Well Matched DACs Extremely Low Analog Ground Current (<60mA/Channel) +10 V Output Swing with +11.4 V Supplies Zero Volt Output Preset (Data = 10 .. 00) Rugged Construction -- Latch-Up Free Parallel Version: MP7611
APPLICATIONS * * * * * * * Data Acquisition Systems ATE Process Control Self-Diagnostic Systems Logic Analyzers Digital Storage Scopes PC Based Controller/DAS
GENERAL DESCRIPTION The MP7610 provides eight independent 14-bit resolution Digital-to-Analog Converters with voltage output amplifiers and a 3-wire standard serial digital address and data port. The output amplifier is capable of sinking and sourcing 5mA, and the output voltage settles to 12-bits in less than 30ms (typ.). The MP7610 is equipped with a serial data (3-wire standard) m-processor logic interface to reduce pin count, package size, and board space. Built using an advanced linear BiCMOS, these devices offer rugged solutions that are latch-up free, and take advantage of EXAR's patented thin-film resistor process which exhibits excellent long term stability and reliability.
SIMPLIFIED BLOCK DIAGRAM
VRP VRP
-+
VRN
D
Q
14
RST XE0 - XE7 Not Used
8 LD 8
LAT0 XR XE XE0
DAC0
+ --
VO0
VRN
14
VRP
D Q LAT7 XR XE XE7 14 DAC7 + --
4 to 16 Decoder SDI LD CLK
D EN LAT Q LAT D Q EN 4
VO7
VRN
D0 to D13 A0 to A3 18-Bit Shift Register
Tri-State Buffer VRP AGND AGND VREF DGND DVDD LD
SDO
VEE
VEE
VCC
VCC
Rev. 4.01
E1998
1 EXAR Corporation, 48720 Kato Road, Fremont, CA 94538 z (510) 668-7000 z (510) 668-7017
MP7610
ORDERING INFORMATION
Package Type
PLCC PLCC PLCC SOIC SOIC SOIC
Temperature Range
0 to +70C --40 to +85C --40 to +85C 0 to +70C --40 to +85C --40 to +85C
Part No.
MP7610CP MP7610BP MP7610AP MP7610CS MP7610BS MP7610AS
Res. (Bits)
14 14 14 14 14 14
INL (LSB)
|2 |4 |8 |4 |2 |8
DNL (LSB)
|2 |3 |4 |3 |2 |4
FSE (LSB)
|16 |24 |32 |24 |16 |32
PIN CONFIGURATIONS
1 AGND VO0 VO1 VO2 VO3 VEE VCC VREF VCC VEE VO4 VO5 VO6 VO7
1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15
See the following page for pin descriptions
DGND N/C N/C DVDD N/C or DVDD N/C SDO SDI CLK LD N/C RST N/C AGND
44 Pin PLCC
28 Pin SOIC (Jedec, 0.346")
Rev. 4.01 2
MP7610
PIN DESCRIPTION
SOIC Pin #
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 1, 8, 10, 11, 14, 16, 17, 22, 23, 25, 27, 28, 30, 33, 35, 36, 38, 39, 41, 42, 43 44 37 40 29 31 32 34 26
PLCC Pin #
2 3 4 5 6 7 9 12 13 15 18 19 20 21 24
Symbol
AGND VO0 VO1 VO2 VO3 VEE VCC VREF VCC VEE VO4 VO5 VO6 VO7 AGND N/C RST N/C LD CLK SDI SDO N/C N/C DVDD N/C N/C
Description
Analog Ground DAC 0 Output DAC 1 Output DAC 2 Output DAC 3 Output Analog Negative Power Supply (--12 V) Analog Positive Power Supply (+12 V) Voltage Reference Input (+5 V) Analog Positive Power Supply (+12 V) Analog Negative Power Supply (--12 V) DAC 4 Output DAC 5 Output DAC 6 Output DAC 7 Output Analog Ground No Connection Reset all DACs to 0 V Output No Connection Load Signal; Load Data to Selected DAC Serial Data Clock Serial Data Input Shift Register Serial Output No Connection No Connection or DVDD Digital Positive Power Supply (+5 V) No Connection No Connection
28
DGND
Digital Ground
Rev. 4.01 3
MP7610
ELECTRICAL CHARACTERISTICS VCC = +12 V, VEE = --12 V, VREF = 5 V, DVDD = 5.0 V, T = 25C, Output Load = 5kW (unless otherwise noted)
Parameter STATIC PERFORMANCE Resolution (All Grades) Integral Non-Linearity (Relative Accuracy) A B C Differential Non-Linearity A B C Positive Full Scale Error A B C Positive Full Scale Error Temperature Coefficient Negative Full Scale Error A B C Negative Full Scale Error Temperature Coefficient Bipolar Zero Offset A B C Bipolar Zero Offset Temperature Coefficient INL Matching A B C N INL |8 |4 |2 DNL |4 |3 |2 +FSE 24 16 12 D+FSE/ DT --FSE 24 16 12 D--FSE/ DT ZOFS |16 |12 |12 DZOFS/ DT DINL |8 |6 |6 |8 |6 |6 LSB |16 |8 |6 |16 |12 |12 DFSE |16 |12 |12 |16 |12 |12 |16 |8 |6 LSB |16 |12 |12 LSB 2 |16 |12 |12 ppm/C LSB 0C to 85C 4 |32 |24 |16 |32 |24 |16 ppm/C LSB 0C to 85C 4 |32 |24 |16 |32 |24 |16 ppm/C LSB 0C to 85C |4 |3 |2.5 LSB |8 |4 |2.5 LSB 14 Bits LSB End Point Linearity Spec Symbol Min 25C Typ Max Tmin to Tmax Min Max Units Test Conditions/Comments
All Channels Maximum Error ME with DAC 0 adjusted to minimum error A B C Bipolar Zero Matching A B C Full Scale Error Matching A B C DZOFS
Rev. 4.01 4
MP7610
ELECTRICAL CHARACTERISTICS (CONT'D)
Parameter DYNAMIC PERFORMANCE Voltage Settling from LD to VDAC Out1 Channel-to-Channel Crosstalk6 Digital Feedthrough1, 6 Power Supply Rejection Ratio REFERENCE INPUTS Impedance of VREF VREF Voltage1, 2 DIGITAL INPUTS3 Logic High Logic Low Input Current Input Capacitance1 ANALOG OUTPUTS Output Swing Output Drive Current Output Impedance Output Short Circuit Current --VEE +1.4 --5 RO ISC VCC --1.4 1 25 30 40 55 5 V mA W mA mA mA mA VIH VIL IL CL 2.4 0.8 10 8 V V mA pF REF VREF 350 3.5 700 1.05k 6 350 1.05k W V See Application Hints for Driving the reference input tsd CT Q PSRR 30 0.04 --70 5 50 50 ms LSB dB ppm/% ZS to FS (20 V Step) 5k, 50pF load DC CLK and Data to VOUTi DVEE & DVCC = 5%, ppm of FS Symbol Min 25C Typ Max Tmin to Tmax Min Max Units Test Conditions/Comments
+FS to AGND +FS to VEE --FS to AGND --FS to VCC
DIGITAL OUTPUTS Output High Voltage Output Low Voltage POWER SUPPLIES VCC Voltage5 VEE Voltage5 DVDD Voltage Positive Supply Current Negative Supply Current Digital Supply Current Power Dissipation ANALOG GROUND CURRENT Per Channel1 DIGITAL TIMING SPECIFICATIONS1,4 Input Clock Pulse Width Data Setup Time Data Hold Time CLK to SDO Propagation Delay DAC Register Load Pulse Width Preset Pulse Width Clock Edge to Load Time LD Falling Edge to SDO Tri-state Enable tCH, tCL tDS tDH tPD tLD tPR tCKLD1 tCKLD2 tHZ1 60 15 15 40 45 65 140 0 50 ns ns ns ns ns ns ns ns IAGND 60 mA See Application Notes VIL = 0, VIH = 5.0, CL = 20 pF VCC VREF+1.5 12 VEE --12.75 --12 DVDD 4.5 5 ICC 8 IEE 15 IDD PDISS 320 12.75 --5 5.5 10 20 2 420 VREF+1.5 12.75 --12.75 --5 4.5 5.5 10 20 2 450 V V V mA mA mA mW VOH VOL 4.5 0.5 V V
Bipolar zero Bipolar zero Bipolar zero Bipolar zero
Note: tLD and tCKLD2 cannot both be min. since tCKLD1=tCKLD2+tLD
Rev. 4.01 5
MP7610
ELECTRICAL CHARACTERISTICS (CONT'D)
Parameter DIGITAL TIMING SPECIFICATIONS1, 4 (CONT'D) LD Rising Edge to SDO Tri-state Disable LD Rising Edge to CLK Enable LD Set-up Time with Respect to CLK tHZ2 tLDCK tLDSU 50 50 45 ns ns ns Symbol Min 25C Typ Max Tmin to Tmax Min Max Units Test Conditions/Comments
NOTES: 1 Guaranteed; not tested. 2 Specified values guarantee functionality. 3 Digital inputs should not go below digital GND or exceed DVDD supply voltage. 4 See Figures 2 and 3. All digital input signals are specified with tR = tF = 10 ns 10% to 90% and timed from a 50% voltage level. 5 For power supply values < |2VREF, the output swing is limited as specified in Analog Outputs. 6 Digital feedthrough and channel-to-channel crosstalk are heavily dependent on the board layout and environment. Specifications are subject to change without notice
ABSOLUTE MAXIMUM RATINGS (TA = +25C unless otherwise noted)1, 2 VCC to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . +16.5 V VEE to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . --16.5 V DVDD to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . +6.5 V VREF to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . +7.0 V AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . +1 V (Functionality guaranteed for |0.5 V only) Digital Input & Output Voltage to DGND . . . . . . . . . . . . . . . . . . . . --0.5 to DVDD +0.5V Analog Inputs & Outputs . . . . . . . Indefinite Shorts to VCC, VEE, DVDD, AGND, DGND (provided that power dissipation of the package spec is not exceeded) Operating Temperature Range Extended Industrial . . . . . . . . . . . . . . --40C to +85C Maximum Junction Temperature . . . --65C to 150C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . 150C Lead Temperature (Soldering, 10 sec) . . . . . +300C Package Power Dissipation Rating @ 75C SOIC, PLCC . . . . . . . . . . . . . . . . . . . . . . . . . . . 1150mW Derates above 75C . . . . . . . . . . . . . . . . . . . . 15mW/C
NOTES: 1 Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation at or above this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. 2 Any input pin which can see a value outside the absolute maximum ratings should be protected by Schottky diode clamps (HP5082-2835) from input pin to the supplies. All inputs have protection diodes which will protect the device from short transients outside the supplies of less than 100mA for less than 100ms.
APPLICATION NOTES
NOTE: When using these DACs to drive remote devices, the accuracy of the output can be improved by utilizing a remote analog ground connection. The difference between the DGND and AGND should be limited to |300 mV to assure normal operation. If there is any chance that the AGND to DGND can be greater than |1 V, we recommend two back-to-back diodes be used between DGND and AGND to clamp the voltage and prevent damage to the DAC. Using a buffer between the remote ground location and AGND may help reduce noise induced from long lead or trace lengths.
Rev. 4.01 6
MP7610
SDI 1 (Data In) 0 CLK 1 0 1 0 1 0 Previous Data DAC Register Loaded A3 (1) MSB A3 A2 A1 A0 D13 D12 D11 D10 D9 D8 D0
LD
SDO
VOUT Note: (1) Because A3 is available immediately after 18th clock edge of DATA Shift-in, only 17 clock cycles are needed to complete the readback.
Figure 1. Serial Data Timing and Loading
SDI
1 0 1 0 1 0 1 0 tCH
tDS
tDH
tHZ1
SDO
tHZ2 HIGH Z tLDCK2
tPD tCKLD2
tLDSU
CLK
tCL
tCKLD1
LD
VOUT
+FS --FS
tLD tSD (1)
+2 LSB Band
Note:
CLK should be high during the falling edge of LD to insure proper function of the shift register.
Figure 2. Serial Data Input Timing (RST = "1")
RST 1 0 VOUT VOUT = 0 V Note: Reset settling time is tPR
Figure 3. Reset Operation
Rev. 4.01 7
MP7610
The MP7610 is equipped with a serial data (3-wire standard)
m-processor logic interface to reduce pin count, package size,
and board wire (space). If the LD signal is high, the CLK signal loads the digital input bits (SDI) into the shift register (4 bits address A3 to A0 plus 14 bits data D13 to D0 for the MP7610). The LD signal going low loads the data into the selected DAC. The
LD signal going low also disables the serial data (SDI), output (SDO tri-stated) and the CLK input. This design tremendously reduces digital noise and glitch transients into the DACs due to free running CLK and SDI. Note also that the preset signal (RST) resets all analog outputs to 0 volt regardless of digital inputs.
Function Shift Data In and Out Stop Shifting Data In and Out Load DACs DAC 0 DAC 1 DAC 2 DAC 3 DAC 4 DAC 5 DAC 6 DAC 7
A3 X X
A2 A1 A0 X X X X X X
LD 1 0
CLK
Repeat
RST 1 1
SDI Data Input Valid X
SDO Data Output Valid Hi-Z
0(R)1 X
0 0 0 0 0 0 0 0 1
0 0 0 0 1 1 1 1 0
0 0 1 1 0 0 1 1 0
0 1 0 1 0 1 0 1 0
No Operation 1(R)0 1(R)0 1(R)0 1(R)0 1(R)0 1(R)0 1(R)0 1(R)0 No Operation No Operation No Operation X
1 1 Reset all DACs to 0 V X
1 1 X
1 1 X
0 1 X
X X X X X X X X X X X X X X
1 1 1 1 1 1 1 1
X X X X X X X X
Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z
1 1 0
X X X
Hi-Z Hi-Z X
Table 1. Digital Function Truth Table Serial In/Serial Out
Note: For timing information See Electrical Characteristics. Output Voltage = 2 * Vr (--1 + 2*D ) (Vr = +5 V) 16384 10 * (--1 + 0) = --10
16382 ) = --1.22 mV 16384 16384
Hex Code OOOO
Binary Code 00000000000000
1FFF 2OOO 2OO1
01111111111111 10000000000000 10000000000001
10 * (--1 +
10 * (--1 +16384 ) = 0 10 * (--1 +16386 ) = 1.22 mV
16384
3FFF
11111111111111
10 * (--1 +32766 ) = 9.99878
16384
Table 2. MP7610 Ideal DAC Output vs. Input Code
Note: See Electrical Characteristics for real system accuracy Rev. 4.01 8
MP7610
SERIAL INTERFACE DIAGRAMS
VRI1 1 8 VOI1 VRI2 1 VOI2 8 VRIn 1 VOIn 8
IC(1)
IC(2)
SDI LD SDO
IC(n)
SDI LD SDO
mPC
Data LD CLK
SDI LD
SDO
Figure 4. Simplified Diagram
VRI1 1 8 VOI1 VRI2 1 8 VOI2 VRIm 1 8 VOIm
IC(1)
IC(2)
SDI LD SDO
IC(n)
SDI LD SDO
mPC
Data Out Data CS or LD CLK n
SDI LD
SDO
#1
#2
#n
Figure 5. Simplified Diagram
VRI1 VOI1 VRI2 VOI2 VRIn VOIn
1 SDO Address Address Decoder n 2
IC(1)
SDI LD SDO1
IC(2)
SDI LD SDO2
IC(n)
SDI LD SDOm
mPC
2n
WR
(SDI) Data In CLK
Figure 6. Simplified Diagram
Rev. 4.01 9
MP7610
A0 to A15 16 3 16 Address Bus
MC6800
E1 02 R/W E3 E2 8
A0 to A2 74LS138 Address Decoder 8 Data Bus
DBO to DB7
DB7
LD SDI RST
CLK
From SYSTEM RESET NOTES 1. Execute consecutive memory write instructions while manipulating the data between WRITEs so that each WRITE presents the next bit. 2. The serial data loading is triggered by the CLK pulse which is asserted by a decoded memory WRITE to memory location 2000, R/W, and 02. A WRITE to address 4000 transfers data from input shift register to DAC register.
Figure 7. MC6800 Interface
8
Address Bus 8 8212 +5 E1 E3 3 A0 to A2 74LS138 Address Decoder
8085
ALE
WR 8 SOD Data Bus
E2
LD SDI RST
CLK
From SYSTEM RESET NOTES: 1. Clock generated by WR and decoding address 8000. 2. Data is clocked in the DAC shift register by executing memory write instructions. The clock input is generated by decoding address 8000 and WR. Data is then loaded into the DAC register with a memory write instruction to address 4000. 3. Serial data must be present in the right justified format in registers H & L of the microprocessor.
Figure 8. 8085 Interface
Rev. 4.01 10
MP7610
PERFORMANCE CHARACTERISTICS
11 V
0V
--11 V VOUT 2.5mV
0V
--2.5mV VOUT Settling 50ms/Division
Graph 1. Typical Output Settling Characteristic VREF = 5 V, RL = 5K, CL = 500pF
Graph 1 shows the typical output settling characteristic of the MP7610 Family for a RESET !ZS!FS!ZS series of code transitions. The top graph shows the output voltage transients, while the bottom graph shows the difference between the output and the ideal output.
4
14-BIT LSB --4 0
CODE
16384
Graph 2. Linearity with VREF = 5 V, All DACs, All Codes
Rev. 4.01 11
MP7610
Graph 3. DAC 0 INL vs. VREF
4 4
Graph 4. DAC 0 DNL vs. VREF
14-BIT LSB
--4
0
CODE
16384
14-BIT LSB --4 0
CODE
16384
Graph 5. DAC 0 Linearity with VREF = 5 V, VOUT = |10
4 4
Graph 6. DAC 0 Linearity with VREF = 4.5 V, VOUT = |9
14-BIT LSB
--4
0
CODE
16384
14-BIT LSB --4 0
CODE
16384
Graph 7. DAC 0 Linearity with VREF = 4 V, VOUT = |8
Rev. 4.01 12
Graph 8. DAC 0 Linearity with VREF = 3.5 V, VOUT = |7
MP7610
VOUT 50 VO I
MP7610 Family
5k
500pF
CL
2mA
CL = 500pF, 5nF, 50nF, 500nF
Figure 9. Circuit for Determining Typical Analog Output Pulse Response
2.0mA
I
0.0 400mV
VO
--400mV 200mV CL = 500pF CL = 5nF
CL = 50nF
CL = 500nF
VOUT
--200mV 0s 1.0ms 2.0ms 3.0ms 4.0ms 5.0ms 6.0ms
Graph 9. Typical Response of the MP7610 Family Analog Output to a Current Pulse with CL=500pF, 5nF, 50nF, 500nF (See Figure 9. above)
Rev. 4.01 13
MP7610
44 LEAD PLASTIC LEADED CHIP CARRIER (PLCC)
Rev. 1.00
D D1 2 1 44 45 x H2 45 x H1
C
Seating Plane A2
B1
D
D1
D3
BD 2
e
D3 A1 A
R
INCHES SYMBOL A A1 A2 B B1 C D D1 D2 D3 e H1 H2 R MIN 0.165 0.090 0.020 0.013 0.026 0.008 0.685 0.650 0.590 MAX 0.180 0.120 ------. 0.021 0.032 0.013 0.695 0.656 0.630
MILLIMETERS MIN 4.19 2.29 0.51 0.33 0.66 0.19 17.40 16.51 14.99 MAX 4.57 3.05 -----0.53 0.81 0.32 17.65 16.66 16.00
0.500 typ. 0.050 BSC 0.042 0.042 0.025 0.056 0.048 0.045
12.70 typ. 1.27 BSC 1.07 1.07 0.64 1.42 1.22 1.14
Note: The control dimension is the inch column
Rev. 4.01 14
MP7610
28 LEAD SMALL OUTLINE (350 MIL JEDEC SOIC)
Rev. 1.00
D
28
15
E
1 14
H
C Seating Plane e B A1 L
A
a
INCHES SYMBOL A A1 B C D E e H L MIN 0.093 0.004 0.013 0.009 0.706 0.340 0.460 0.016 0 MAX 0.104 0.012 0.020 0.013 0.718 0.350 0.485 0.050 8
MILLIMETERS MIN 2.35 0.10 0.33 0.23 17.93 8.64 11.68 0.40 0 MAX 2.65 0.30 0.51 0.32 18.24 8.89 12.32 1.27 8
0.050 BSC
1.27 BSC
a
Note: The control dimension is the millimeter column
Rev. 4.01 15
MP7610
NOTICE EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration purposes and may vary depending upon a user's specific application. While the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies. EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circumstances. Copyright 1998 EXAR Corporation Datasheet June 1998 Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.
Rev. 4.01 16

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